1. Technical Field
This invention relates generally to thermal ink jet printing and particularly to a novel thermal ink jet printhead and a method to fabricate the printhead by integrating ink jet resistor devices with driver pulse MOS devices on the same chip within the printhead using a unique vertically stacked structure.
2. Background Art
The concepts of thermal ink jet printing have been described in a variety of journals. The Hewlett Packard Journal, in particular, in the May 1985 and the August 1988 editions, provides excellent descriptions of the ink jet printing concepts as well other topics related to manufacture of print heads, color ink jet printer heads, and second generation ink jet chip structures.
FIG. 1 shows a prior art thermal ink jet structure. The ink jet is disposed on a silicon substrate 11 with a thin thermal silicon oxide layer 10.
In the fabrication of a thermal ink jet printhead, the basic thermal ink jet device structure is a heater area 16 consisting of an aluminum or aluminum-copper metal line 19 over a resistor 17 made of a resistive material such as tantalum-aluminum or hafnium diboride. Both the resistor 17 and the metal 19 lines are defined using standard photolithography processes. Deposition of the resistive and metal films can be accomplished using sputtering or, as in the case of the aluminum and copper, evaporation. The aluminum metal lines carry a current pulse across each of the resistors.
Once the resistors 17 and metal lines 19 are defined, it is known to deposit a silicon nitride or silicon carbide film 21 to act as a barrier layer to provide protection for the heater resistor structures from chemical attack by the ink. Typically, the ink is stored in a reservoir behind the ink jet chip and is transported through an access hole to a secondary reservoir area over the barrier layer covering the heater region 16 by gravity and capillary action. Also known is an organic overcoat 25 which further enhances protection for the heater resistors 16 from the ink. These barrier layers 21, 25 are very important because of the corrosive nature of the ink. Therefore, they must be chemically inert and highly impervious to the ink. Once the barrier layers have been deposited, the chip is ready for placement in the printhead. Typically, connection to the other electronic circuitry in the printer is provided using a flex circuit connected to an interconnect pad 29. Among the printer circuitry are the driver pulse circuits which fire the heater resistors.
The primary function of the driver circuitry is to step up the input voltage from the power supply. Typically, these integrated drive circuitry chips contain either a combination of bipolar and MOS devices such as BiMOS II or contain all MOS devices. The BiMOS circuitry can be configured to make bipolar open-collector Darlington outputs, data latches, shift register, and control circuitry.
There is ongoing interest in ink jet printhead fabrication in the continued integration of functions within the printhead. This is driven, as in all cases of electronics integration, by space considerations. If the overall electronics and size of the printer can be reduced, costs of the printer can be reduced. Such integration is alluded to in a number of patents. Hess, in U.S. Pat. No. 4,719,477, outlines a method by which ink jet devices could be interconnected to driver pulse circuitry via a multi-level metallization scheme. Hawkins, in U.S Pat. No. 4,532,530, using a polysilicon resistor material, mentions simultaneous fabrication of the both the ink jet resistor and interconnection with related MOS circuitry. Along similar lines in Bassous et al., U.S. Pat. No. 3,949,410, describe the ". . . representation of the circuitry for achieving the synchronization signal established integral with the silicon block in accordance with integrated semiconductor circuit processing procedures".
However, none of the schemes presented in the prior art provided for the vertical integration of the pulse driver circuitry with the ink jet resistors. The prior art schemes call for horizontal or lateral methods to integrate functions which greatly increases the chip size, and therefore, cost of fabrication. While one could shrink the dimensions of the MOS driver circuitry to ameliorate the growth in chip size, it is the experience in semiconductor processing that smaller dimensions lead to lower percentage yields, i.e., greater costs.